1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a buried local interconnect structure for connecting components of an integrated circuit, and to a method of making the same.
2. Description of the Related Art
Modem integrated circuits routinely contain millions of individual transistors and other electronic components. Most of the interconnections for the numerous components in such circuits are provided via one or more metallization layers that serve as global interconnect levels. Each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required.
In addition to the one or more metallization layers, modem integrated circuits also incorporate numerous routing restricted interconnect levels commonly known as local interconnects ("LI"). LIs are used for short conductor runs such as those that locally interconnect gates and drains in NMOS and CMOS circuits and those that connect a given metallization layer to a particular structure in the integrated circuit.
A conventional method frequently employed to form LI structures involves a damascene process in which the substrate containing the integrated circuit is coated with a layer of dielectric material, such as a silicon dioxide or tetrathyl-ortho-silicate ("TEOS") passivation layer. The passivation layer is lithographically patterned and etched to form trenches where the LI structures will be deposited. In another conventional processing technique, local interconnects are formed on the substrate prior to application of a passivation layer. A feature common to both conventional techniques is the disposition of the local interconnect layers at or above the silicon-silicon dioxide interface.
As with many other modem semiconductor processing techniques, there are tradeoffs associated with implementing local interconnect layers. LI's provide a vital tool for VLSI and ULSI circuit designers. The ability to pattern pluralities of short conductor runs has enabled designers to save significant chip-area in integrated circuit layouts. At the same time, each local interconnect layer formed above the silicon-silicon dioxide interface in a give integrated circuit represents a potential restriction on the routing of other conductor lines, and thus the packing density, for the circuit.
The problem of routing restriction is more complex when doped polysilicon is used as the local interconnect material. Doped polysilicon is often selected for local interconnect layers as a result of thermal budgeting or other design considerations. The poly is commonly used as both a gate material and local interconnect material. As a result, when the polysilicon layer functions as an interconnect structure, it cannot cross over regions where a transistor gate exists without making contact to the gate. Unless such contacts with the gates are desired, gate locations represent areas on the substrate that cannot be crossed by polysilicon layers where these layers are being used as local interconnect layers.
Various techniques to overcome the polysilicon routing restrictions have been implemented in the past. Some of these include selectively forming TiSi.sub.2 to form an LI level, sputter-depositing titanium-tungsten over CoSi.sub.2 contacts, forming a titanium nitride layer over a TiSi.sub.2 contact, and forming a dual-doped polysilicon LI with diffused source/drain junctions. While these techniques alleviate some of the routing difficulties associated with polysilicon local interconnect layers, they also increase processing steps and complexity. Furthermore, cluttering of the substrate area above the silicon-silicon dioxide interface remains a problem.
The present invention is directed to overcoming or reducing one or more of the foregoing disadvantages.